1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to the method of manufacturing a crown-shaped dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
Memory is a type of semiconductor devices for registering data and storing numerical information. As microprocessors become more powerful functionally and the amount of software data that needs to be processed becomes very large, the amount of memory necessary for storing the data is also correspondingly greater. In order to satisfy the need for storing large amount of data, production of memory cells that can have a higher level of integration is the driving force behind some of the newly developed techniques in semiconductor manufacture. DRAM is now an extensively used integrated circuit device for data storage.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in the fabrication of a conventional DRAM capacitor. First, as shown in FIG. 1A, a substrate 10 having a transistor (not shown) already formed thereon is provided. Next, a low pressure chemical vapor deposition (LPCVD) method is used to deposit a layer of insulating material over the substrate 10 and the transistor. The insulating layer can be a silicon dioxide layer or a silicon nitride layer. Then, conventional photolithographic and etching techniques are used to pattern the layer of insulating material to form an insulating layer 12 and a contact opening exposing one source/drain region (not shown) of the transistor. Thereafter, a low pressure chemical vapor deposition method is used to deposit a layer of conductive material over the insulating layer 12 and into the contact opening covering the source/drain region (not shown) to form a conductive layer 14a. The conductive material can be an impurities-doped polysilicon layer having a thickness preferably of about 0.5 to 1.5 .mu.m.
Next, as shown in FIG. 1B, conventional photolithographic and etching techniques are used to pattern the conductive layer 14a to form a conductive layer 14b. Subsequently, a hemispherical grained silicon layer 16a is formed over the conductive layer 14b and the insulating layer 12. A low pressure chemical vapor deposition method is used to deposit the hemispherical grained silicon. During the reaction, silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) is used as the gaseous source and a temperature between the growth of amorphous silicon and polysilicon is maintained. For example, for silane the temperature is about 550.degree. C. to 590.degree. C. for the direct deposition of silicon.
Next, as shown in FIG. 1C, an anisotropic etching method is used to remove the hemispherical grained silicon above the insulating layer 12 forming a hemispherical grained silicon layer 16b. The hemispherical grained silicon layer 16b and the conductive layer 14b together constitute the lower electrode of a capacitor.
Next, as shown in FIG. 1D, a dielectric layer is formed covering the lower electrode. The dielectric layer 18 can have, for example, an oxide/nitride/oxide triple-layered structure, and deposits by using a low pressure chemical vapor deposition method. Thereafter, a layer of conductive material is deposited over the dielectric layer 18 to form the upper electrode 19 of the capacitor. The conductive layer can be, example, an impurities-doped polysilicon layer formed by using a low pressure chemical vapor deposition method.
However, in the step of etching to remove the hemispherical grained silicon layer above the insulating layer 12 as shown in FIG. 1C, the hemispherical grained silicon layer above the conductive layer 14b will also be removed. Hence, there is the possibility that the conductive layer 14b can be over-etched leading to the formation of spikes (as shown in FIG. 1C). These spikes can easily cause serious current leakage problems, and may affect the operation of the DRAM considerably. Furthermore, surface area produced by the conventional techniques is small, and so the corresponding capacitance of the capacitor is small. In addition, the height 17 of the capacitor produced by a conventional method is rather high, which can lead to processing problems due to the large step height that exists relative to the surrounding areas.
In light of the foregoing, there is a need in the art to provide an improved method of forming DRAM capacitor.